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flash memory 1 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c K9K1208Q0C k9k1216q0c document title 64m x 8 bit , 32m x 16 bit nand flash memory revision history the attached datasheets are prepared and approved by samsung el ectronics. samsung el ectronics co., ltd. reserve the right to change the specifications. sams ung electronics will evaluate and reply to y our requests and questions about device. if you h ave any questions, please contact the samsung branch office near you. revision no. 0.0 1.0 2.0 2.1 2.2 2.3 2.4 2.5 remark advance preliminary preliminary history initial issue. 1.pin assignment of tbga dummy ball is changed. (before) dnu --> (after) n.c 2. add the rp vs tr ,tf & rp vs ibusy graph for 1.8v device (page 34) 3. add the data protection vcc guidence for 1.8v device - below about 1.1v. (page 35) 4. add the specification of block lock scheme.(page 29~32) 5. pin assignment of tbga a3 ball is changed. (before) n.c --> (after) vss 1. the maximum operating current is changed. read : icc1 20ma-->30ma program : icc2 20ma-->40ma erase : icc3 20ma-->40ma the min. vcc value 1. 8v devices is changed. k9k12xxq0c : vcc 1.65v~1.95v --> 1.70v~1.95v pb-free package is added. k9k1208u0c-hcb0,hib0 k9k12xxq0c-hcb0,hib0 k9k1216u0c-hcb0,hib0 k9k1216q0c-hcb0,hib0 errata is added.(front page)-k9k12xxq0c twc twp trc treh trp trea tcea specification 45 25 50 15 25 30 45 relaxed value 60 40 60 20 40 40 55 1. max. thickness of tbga packge is changed. 0.09 0.10 (before) --> 1.10 0.10 (after) 2. new definition of the number of invalid blocks is added. (minimum 1004 valid blocks are guaranteed for each contiguous 128mb memory space.) 1. the guidence of lockpre pin usage is changed. don?t leave it n.c. not using lock mechanism & power-on auto- read, connect it vss.(before) --> not using lock mechanism & power-on auto-read, connect it vss or leave it n.c(after) 2. 2.65v device is added. 3. note is added. (vil can undershoot to -0.4v and vih can overshoot to vcc +0.4v for durations of 20 ns or less.) draft date sep. 12th 2002 jan. 3rd 2003 jan. 17th 2003 mar. 5th 2003 mar. 13rd 2003 mar. 17th 2003 apr. 4th 2003 jul. 4th 2003 note : for more detailed features and specifications in cluding faq, please refer to samsung?s flash web site. http://www.samsung.com/products /semiconductor/flash/technicalinfo/datasheets.htm
flash memory 2 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c K9K1208Q0C k9k1216q0c revision history the attached datasheets are prepared and approved by samsung el ectronics. samsung el ectronics co., ltd. reserve the right to change the specifications. sams ung electronics will evaluate and reply to y our requests and questions about device. if you h ave any questions, please contact the samsung branch office near you. revision no. 2.6 2.7 2.8 2.9 3.0 remark history 1. trea value of 1.8v device is changed. k9k12xxq0c : trea 30ns --> 35ns 2. errata is deleted. 1. command table is edited. 2. ac parameters are changed. twc twh twp trc treh trp trea tcea k9k12xxu0c k9k12xxd0c 50 15 25 50 15 25 30 45 k9k12xxq0c 60 20 40 60 20 40 40 55 1. ac parameters are changed. twc twh twp trc treh trp trea tcea K9K1208Q0C 50 15 25 50 15 25 35 45 k9k1216q0c 60 20 40 60 20 40 40 55 1. the test condition for stand-by currents are changed. i sb 1: ce =v ih , wp =0v/v cc -->> ce =v ih , wp =lockpre=0v/v cc isb2: ce =v cc -0.2, wp =0v/v cc -->> ce =v cc -0.2, wp =lockpre=0v/v cc 1. nand flash technical notes is changed. -invalid block -> in itial invalid block ( page 14 ) -error in write or read operation ( page 15 ) -program flow chart ( page 15 ) 2. tbga->fbga draft date aug. 20th. 2003 oct. 28th. 2003 dec. 17th. 2003 apr. 22th 2004 oct. 25th. 2004 note : for more detailed features and specifications in cluding faq, please refer to samsung?s flash web site. http://www.samsung.com/products /semiconductor/flash/technicalinfo/datasheets.htm document title 64m x 8 bit , 32m x 16 bit nand flash memory
flash memory 3 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c K9K1208Q0C k9k1216q0c general description features ? voltage supply - 1.8v device(k9k12xxq0c) : 1.70~1.95v - 2.65v device(k9f12xxd0c) : 2.4~2.9v - 3.3v device(k9k12xxu0c) : 2.7 ~ 3.6 v ? organization - memory cell array - x8 device(k9k1208x0c) : (64m + 2048k)bit x 8 bit - x16 device(k9k1216x0c) : (32m + 1024 k)bit x 16bit - data register - x8 device(k9k1208x0c) : (512 + 16)bit x 8bit - x16 device(k9k1216x0c) : (256 + 8)bit x16bit ? automatic program and erase - page program - x8 device(k9k1208x0c) : (512 + 16)byte - x16 device(k9k1216x0c) : (256 + 8)word - block erase : - x8 device(k9k1208x0c) : (16k + 512)byte - x16 device(k9k1216x0c) : ( 8k + 256)word ? page read operation - page size - x8 device(k9k1208x0c) : (512 + 16)byte - x16 device(k9k1216x0c) : (256 + 8)word - random access : 10 s(max.) - serial page access : 50ns(min.)* *k9k1216q0c : 60ns(min.) 64m x 8 bit / 32m x 16 bit nand flash memory ? fast write cycle time - program time : 200 s(typ.) - block erase time : 2ms(typ.) ? command/address/data multiplexed i/o port ? hardware data protection - program/erase lockout during power transitions ? reliable cmos floating-gate technology - endurance : 100k program/erase cycles - data retention : 10 years ? command register operation ? intelligent copy-back ? unique id for copyright protection ? package - k9k12xxx0c-gcb0/gib0 63- ball fbga ( 9 x 11 /0.8mm pitch , width 1.2 mm) - k9k12xxx0c-jcb0/jib0 63- ball fbga ( 9 x 11 /0.8mm pitch , width 1.2 mm) - pb-free package offered in 64mx8bit or 32mx16bit, the k9k12xxx0c is 512m bit with spare 16m bit capacity. the device is offered in 1.8v, 2.65v , 3.3v vcc. its nand cell provides the most cost-effective solution for the solid state mass storage market. a program operatio n can be performed in typical 200 s on the 528-byte(x8 device) or 264-word(x16 device) page and an erase operation can be performed in typical 2ms on a 16k-byte(x8 device) or 8k-word(x16 device) block. data in the page can be read out at 50ns(k9k1216q0c : 60ns) cycle time per byte (x8 dev ice) or word(x16 device). the i/o pins serve as the ports for address and data input/output as well as command input. the on-chip write control automates all program and erase functions including pulse repetition, where require d, and internal verification and margining of data. even the writ e-intensive systems can take advantage of the k9k12xxx0c s extended reliability of 100k program/erase cycles by providing ecc( error correcting code) with real time mapping-out algorithm. the k9k12xxx0c is an optimum solution for large nonvolatile st orage applications such as soli d state file storage and other por table applications requiring non-volatility. product list. part number vcc range organization pkg type K9K1208Q0C-g,j 1.70 ~ 1.95v x8 fbga k9k1216q0c-g,j x16 k9k1208d0c-g,j 2.4 ~ 2.9v x8 k9k1216d0c-g,j x16 k9k1208u0c-g,j 2.7 ~ 3.6v x8 k9k1216u0c-g,j x16
flash memory 4 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c K9K1208Q0C k9k1216q0c k9k12xxx0c-gcb0 ,jcb0/gib0,jib0 x16 x8 pin configuration (fbga) 63-ball fbga (measured in millimeters) package dimensions 9.00 0.10 #a1 side view top view 1.20 (max.) 0.45 0.05 4321 a b c d g bottom view 11.00 0.10 63- ? 0.45 0.05 0.80 x7= 5.60 11.00 0.10 0.80 x5= 4.00 0.80 0.25 (min.) 0.10max b a 2.80 2.00 9.00 0.10 (datum b) (datum a) 0.20 m a b ? 0.80 0.80 x11= 8.80 0.80 x9= 7.20 65 9.00 0.10 e f h (top view) (top view) r/b /we /ce vss ale /wp /re cle nc nc nc nc vcc nc nc i/o0 i/o1 nc nc vccq i/o5 i/o7 vss i/o6 i/o4 i/o3 i/o2 vss nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc lockpre nc nc n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c r/b /we /ce vss ale /wp /re cle i/o7 i/o5 i/o12 io14 vcc i/o10 i/o8 i/o1 i/o9 i/o0 i/o3 vccq i/o6 i/o15 vss i/o13 i/o4 i/o11 i/o2 vss nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc lockpre nc nc 3456 1 2 a b c d g e f h 3456 1 2 a b c d g e f h
flash memory 5 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c K9K1208Q0C k9k1216q0c pin description note : connect all v cc and v ss pins of each device to common power supply outputs. do not leave v cc or v ss disconnected. pin name pin function i/o 0 ~ i/o 7 (k9k1208x0c) i/o 0 ~ i/o 15 (k9k1216x0c) data inputs/outputs the i/o pins are used to input command, address and data, and to output data during read operations. the i/ o pins float to high-z when the chip is deselected or when the outputs are disabled. i/o8 ~ i/o15 are used only in x16 orga nization device. since command input and address input are x8 oper- ation, i/o8 ~ i/o15 are not used to input command & address. i/o8 ~ i/o15 are used only for data input and output. cle command latch enable the cle input controls the activating path for comma nds sent to the command register. when active high, commands are latched into the command register through the i/o ports on the rising edge of the we signal. ale address latch enable the ale input controls the activating path for addres s to the internal address registers. addresses are latched on the rising edge of we with ale high. ce chip enable the ce input is the device selection control. when the device is in the busy state, ce high is ignored, and the device does not return to standby mode in program or erase operation. regarding ce control during read operation, refer to ?page read? section of device operation . re read enable the re input is the serial data-out control, and when acti ve drives the data onto t he i/o bus. data is valid trea after the falling edge of re which also increments the inter nal column address counter by one. we write enable the we input controls writes to the i/o port. comm ands, address and data are latched on the rising edge of the we pulse. wp write protect the wp pin provides inadvertent write/erase protection during power tra nsitions. the internal high voltage generator is reset when the wp pin is active low. when lockpre is a logic high and wp is a logic low, the all blocks go to lock state. r/b ready/busy output the r/b output indicates the status of the device operation. when low, it indicates that a program, erase or random read operation is in process and returns to hi gh state upon completion. it is an open drain output and does not float to high-z condition when the ch ip is deselected or when outputs are disabled. vcc q output buffer power vcc q is the power supply for output buffer. vcc q is internally connected to vcc, thus should be biased to vcc. vcc power v cc is the power supply for device. vss ground n.c no connection lead is not internally connected. dnu do not use leave it disconnected lockpre lock mechanism & power-on auto-read enable to enable and disable the lock mec hanism and power on auto read. when lockpre is a logic high, block lock mode and power-on auto-read mode are enabled, and when lockpre is a logic low, block lock mode and power-on auto-read mode are disabled. power-on auto-read mode is available only on 3.3v device(k9k12xxu0c) not using lock mechanism & power-on auto-read, connect it vss or leave it n.c
flash memory 6 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c K9K1208Q0C k9k1216q0c 512byte 16 byte figure 1-1. k9k1208x0c (x8) functional block diagram figure 2-1. k9k1208x0c (x8) array organization v cc x-buffers 512m + 16m bit command nand flash array (512 + 16)byte x 131072 y-gating page register & s/a i/o buffers & latches latches & decoders y-buffers latches & decoders register control logic & high voltage generator global buffers output driver v ss a 9 - a 25 a 0 - a 7 command ce re we wp i/0 0 i/0 7 v cc/ v ccq v ss a 8 1st half page register (=256 bytes) 2nd half page register (=256 bytes) 128k pages (=4,096 blocks) 512 byte 8 bit 16 byte 1 block =32 pages = (16k + 512) byte i/o 0 ~ i/o 7 1 page = 528 byte 1 block = 528 byte x 32 pages = (16k + 512) byte 1 device = 528bytes x 32pages x 4,096 blocks = 528 mbits page register cle ale column address row address (page address) note : column address : starting address of the register. 00h command(read) : defines the starting address of the 1st half of the register. 01h command(read) : defines the starting address of the 2nd half of the register. * a 8 is set to "low" or "high" by the 00h or 01h command. * l must be set to "low". * the device ignores any additional input of address cycles than reguired. i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 1st cycle a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 2nd cycle a 9 a 10 a 11 a 12 a 13 a 14 a 15 a 16 3rd cycle a 17 a 18 a 19 a 20 a 21 a 22 a 23 a 24 4th cycle a 25 *l *l *l *l *l *l *l
flash memory 7 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c K9K1208Q0C k9k1216q0c 256word 8 word figure 2-2. k9k1216x0c (x16) array organization page register (=256 words) 128k pages (=4,096 blocks) 256 word 16 bit 8 word 1 block =32 pages = (8k + 256) word i/o 0 ~ i/o 15 1 page = 264 word 1 block = 264 word x 32 pages = (8k + 256) word 1 device = 264words x 32pages x 4096 blocks = 528 mbits page register figure 1-2. k9k1216x0c (x16) functional block diagram v cc x-buffers 512m + 16m bit command nand flash array (256 + 8)word x 131072 y-gating page register & s/a i/o buffers & latches latches & decoders y-buffers latches & decoders register control logic & high voltage generator global buffers output driver v ss a 9 - a 25 a 0 - a 7 command ce re we wp i/0 0 i/0 15 v cc/ v ccq v ss cle ale note : column address : starting address of the register. * l must be set to "low". * the device ignores any additional i nput of address cycles than reguired. i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o8 to 15 1st cycle a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 l* 2nd cycle a 9 a 10 a 11 a 12 a 13 a 14 a 15 a 16 l* 3rd cycle a 17 a 18 a 19 a 20 a 21 a 22 a 23 a 24 l* 4th cycle a 25 l* l* l* l* l* l* l* l* column address row address (page address)
flash memory 8 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c K9K1208Q0C k9k1216q0c product introduction the k9k12xxx0c is a 528mbit(553,648,218 bit) memory organized as 131,072 rows(pages) by 528(x8 device) or 264(x16 device) columns. spare eight columns are located from column addres s of 512~527(x8 device) or 256~263(x16 device). a 528-byte(x8 device) or 264-word(x16 device) data register is connected to memory cell arrays accommodating data transfer between the i/o bu ff- ers and memory during page read and page program operations. the me mory array is made up of 16 cells that are serially con- nected to form a nand structure. each of the 16 cells resides in a different page. a block consists of two nand structured str ings. a nand structure consists of 16 cells. total 135168 nand cells resi de in a block. the array organization is shown in figure 2-1,2 -2. the program and read operations are executed on a page basis, whil e the erase operation is executed on a block basis. the memor y array consists of 4096 separately erasable 16k-byte(x8 device) or 8k-word(x16 device) blocks. it indicates that the bit by bit erase operation is prohibited on the k9k12xxx0c. the k9k12xxx0c has addresses multiplexed into 8 i/os(x16 device case : lower 8 i/os). k9k1216x0c allows sixteen bit wide data transport into and out of page registers. this scheme dramatic ally reduces pin count s while providing high performance and allo ws systems upgrades to future densities by main taining consistency in syst em board design. command, address and data are all writt en through i/o s by bringing we to low while ce is low. data is latched on the rising edge of we . command latch enable(cle) and address latch enable(ale) are used to multiplex command and addr ess respectively, via the i/o pins. some commands require one bus cycle. for example, rese t command, read command, status read command, etc require just one cycle bus. some other com- mands like page program and copy-back program and block erase, require three cycles: one cycle for setup and the other cycle fo r execution. the 32m-byte(x8 device) or 16m-word(x16 devi ce) physical space requires 25 addresses(x8 device) or 24 addresses(x16 device), thereby r equiring four cycles for word-level addressing : column address, low row address and high row address, in that order. page read and page program need the same four address cycles following the required command input. in block erase operation, however, only the thr ee row address cycles are used. device oper ations are selected by writing specific com- mands into the command register. table 1 defi nes the specific commands of the k9k12xxx0c. the device includes one block siz ed otp(one time programmable), which can be used to increase system security or to provide identification capabilities. detailed informat ion can be obtained by contact with samsung. table 1. command sets note : 1. the 01h command is available only on x8 device(k9k1208x0c). caution : any undefined command inputs are prohibited except for above command set of table 1. function 1st. cycle 2nd. cycle acceptable command during busy read 1 00h/01h (1) - read 2 50h - read id 90h - reset ffh - o page program 80h 10h copy-back program 00h 8ah lock 2ah - unlock 23h 24h lock-tight 2ch - read block lock status 7ah - block erase 60h d0h read status 70h - o
flash memory 9 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c K9K1208Q0C k9k1216q0c recommended operating conditions (voltage reference to gnd, k9k12xxx0c-gcb0,jcb0 : t a =0 to 70 c, k9k12xxx0c-gib0,jib0 : t a =-40 to 85 c) parameter symbol k9k12xxq0c(1.8v) k9k12xxd0c(2.65v) k9k12xxu0c(3.3v) unit min typ. max min typ. max min typ. max supply voltage v cc 1.70 1.8 1.95 2.4 2.65 2.9 2.7 3.3 3.6 v supply voltage v ccq 1.70 1.8 1.95 2.4 2.65 2.9 2.7 3.3 3.6 v supply voltage v ss 000000000 v absolute maximum ratings note : 1. minimum dc voltage is -0.6v on input/output pins. during tran sitions, this level may undershoo t to -2.0v for periods <30ns. maximum dc voltage on input/output pins is v cc, +0.3v which, during transitions, may overshoot to v cc +2.0v for periods <20ns. 2. permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rati ng conditions for extended peri ods may affect reliability. parameter symbol rating unit 1.8v device 3.3v/2.65v device voltage on any pin relative to v ss v in/out -0.6 to + 2.45 -0.6 to + 4.6 v v cc -0.2 to + 2.45 -0.6 to + 4.6 v ccq -0.2 to + 2.45 -0.6 to + 4.6 temperature under bias k9k12xxx0c-xcb0 t bias -10 to +125 c k9k12xxx0c-xib0 -40 to +125 storage temperature k9k12xxx0c-xcb0 t stg -65 to +150 c k9k12xxx0c-xib0 short circuit current ios 5 ma
flash memory 10 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c K9K1208Q0C k9k1216q0c dc and operating characteristics (recommended operating cond itions otherwise noted.) parameter symbol test conditions k9k12xxx0c unit 1.8v 2.65v 3.3v min typ max min typ max min typ max operat- ing current sequential read i cc 1 trc=50ns, ce =v il i out =0ma -1020 -1020-1030 ma program i cc 2- -1020-1020-1040 erase i cc 3- -1020-1020-1040 stand-by current(ttl) i sb 1 ce =v ih , wp =lockpre=0v/v cc --1--1--1 stand-by cur- rent(cmos) i sb 2ce =v cc -0.2, wp =lockpre=0v/v cc -1050 -1050-1050 a input leakage current i li v in =0 to vcc(max) - - 10 - - 10 - - 10 output leakage current i lo v out =0 to vcc(max) - - 10 - - 10 - - 10 input high voltage v ih* i/o pins v ccq -0.4 - v ccq +0.3 v ccq -0.4 - v ccq +0.3 2.0 - v ccq +0.3 v except i/o pins v cc -0.4 - vcc +0.3 v cc -0.4 - v cc +0.3 2.0 - v cc +0.3 input low voltage, all inputs v il* - -0.3 - 0.4 -0.3 - 0.5 -0.3 - 0.8 output high voltage level v oh k9k12xxq0c :i oh =-100 a k9k12xxd0c :i oh =-100 a k9k12xxu0c :i oh =-400 a v ccq -0.1 -- v ccq -0.4 --2.4-- output low voltage level v ol k9k12xxq0c :i ol =100ua k9k12xxd0c :i ol =100 a k9k12xxu0c :i ol =2.1ma - - 0.1 - - 0.4 - - 0.4 output low current(r/b )i ol (r/b ) k9k12xxq0c :v ol =0.1v k9k12xxd0c :v ol =0.1v k9k12xxu0c :v ol =0.4v 34 - 34-810-ma
flash memory 11 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c K9K1208Q0C k9k1216q0c capacitance ( t a =25 c, v cc =1.8v/2.65v/3.3v, f=1.0mhz) note : capacitance is periodically sampled and not 100% tested. item symbol test condition min max unit input/output capacitance c i/o v il =0v - 20 pf input capacitance c in v in =0v - 20 pf valid block note : 1. the device may include invalid blo cks when first shipped. additional invalid blocks may develop while being used. the number of valid blo cks is pre- sented with both cases of invalid blocks considered. invalid bl ocks are defined as blocks that contain one or more bad bits . do not erase or program factory-marked bad blocks. refer to the attached technica l notes for a appropriate management of invalid blocks. 2. the 1st block, which is placed on 00h bloc k address, is guaranteed to be a valid bloc k, does not require error correction u p to 1k program/erase cycles. 3. minimum 1004 valid blocks are guaranteed for each contiguous 128mb memory space. parameter symbol min typ. max unit valid block number n vb 4026 - 4096 blocks ac test condition (k9k12xxx0c-gcb0,jcb0 :ta=0 to 70 c, k9k12xxx0c-gib0,jcb0 :ta=-40 to 85 c k9k12xxq0c : vcc=1.70v~1.95v , k9k12xxd0c : vcc=2.4v ~2.9v , k9k12xxu0c : vcc=2.7v~3.6v unless otherwise noted) parameter k9k12xxq0c k9k12xxd0c k9k12xxu0c input pulse levels 0v to vcc q 0v to vcc q 0.4v to 2.4v input rise and fall times 5ns 5ns 5ns input and output timing levels vcc q /2 vcc q /2 1.5v k9k12xxq0c:output load (vcc q :1.8v +/-10%) k9k12xxd0c:output load (vcc q :2.65v +/-10%) k9k12xxu0c:output load (vcc q :3.0v +/-10%) 1 ttl gate and cl=30pf 1 ttl gate and cl=30pf 1 ttl gate and cl=50pf k9k12xxu0c:output load (vcc q :3.3v +/-10%) - - 1 ttl gate and cl=100pf mode selection note : 1. x can be v il or v ih. 2. wp should be biased to cmos high or cmos low for standby. cle ale ce we re lockpre wp mode hll h x x read mode command input l h l h x x address input(4clock) hll h x h write mode command input l h l h x h address input(4clock) l l l h x h data input l l l h x x data output x x x x h x x during read(busy) on the devices x x x x x x h during program(busy) x x x x x x h during erase(busy) x x (1) x x x x l write protect xxhxx 0v/v cc (2 0v/v cc (2) stand-by
flash memory 12 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c K9K1208Q0C k9k1216q0c program/erase characteristics parameter symbol min typ max unit program time t prog - 200 500 s dummy busy time for the lock or lock-tight block t lbsy -510 s number of partial program cycles in the same page main array nop --2cycles spare array - - 3 cycles block erase time t bers -23ms ac timing characteristics for command / address / data input note : 1. if tcs is set less than 10ns, twp must be minimum 35ns, otherwise, twp may be minimum 25ns. parameter symbol min max unit k9k1208x0c k9k12xxd0c k9k12xxu0c k9k1216q0c k9k1208x0c k9k12xxd0c k9k12xxu0c k9k1216q0c cle setup time t cls 00 - -ns cle hold time t clh 10 10 - - ns ce setup time t cs 00 - -ns ce hold time t ch 10 10 - - ns we pulse width t wp 25 (1) 40 - - ns ale setup time t als 00 - -ns ale hold time t alh 10 10 - - ns data setup time t ds 20 20 - - ns data hold time t dh 10 10 - - ns write cycle time t wc 50 60 - - ns we high hold time t wh 15 20 - - ns
flash memory 13 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c K9K1208Q0C k9k1216q0c ac characteristics for operation note : 1. k9f5608q0c trea = 35ns. 2. if reset command(ffh) is written at ready state, the device goes into busy for maximum 5us. parameter symbol min max unit k9k1208x0c k9k12xxd0c k9k12xxu0c k9k1216q0c k9k1208x0c k9k12xxd0c k9k12xxu0c k9k1216q0c data transfer from cell to register t r --1010 s ale to re delay t ar 10 10 - - ns cle to re delay t clr 10 10 - - ns ready to re low t rr 20 20 - - ns re pulse width t rp 25 40 - - ns we high to busy t wb - - 100 100 ns read cycle time t rc 50 60 - - ns re access time t rea -- 30/35 (1) 40 ns ce access time t cea - - 45 55 ns re high to output hi-z t rhz - - 30 30 ns ce high to output hi-z t chz - - 20 20 ns re or ce high to output hold t oh 15 15 - - ns re high hold time t reh 15 20 - - ns output hi-z to re low t ir 00 - -ns we high to re low t whr1 60 60 - - ns we high to re low in block lcok t whr2 100 100 - - ns device resetting time (read/program/erase) t rst - - 5/10/500 (2) 5/10/500 (2) s
flash memory 14 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c K9K1208Q0C k9k1216q0c nand flash technical notes identifying initial invalid block(s) initial invalid block(s) initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by samsung. the information regarding the initial invali d block(s) is so called as the initial invalid block information. devices with init ial invalid block(s) have the same quality level as devi ces with all valid blocks and have the same ac and dc characteristics. an initial i nvalid block(s) does not affect the performance of valid block(s) because it is isolated fr om the bit line and the common source line by a select transistor. the system design must be able to mask out t he initial invalid block(s) via ad dress mapping. the 1st block, which is placed on 00h block address, is guaranteed to be a valid block, does not require error correction up to 1k program/erase cycle s. all device locations are erased(ffh ) except locations where the initial invalid bl ock(s) information is written prior to shippi ng. the initial invalid block(s) status is defined by the 6th byte(x8 device) or 1st word(x16 device) in the spare area. samsung makes sure that either the 1st or 2nd page of every initial invalid bloc k has non-ffh(x8 device) or non-ffffh(x16 device) data at the colu mn address of 517(x8 device) or 256 and 261(x16 device). since the in itial invalid block information is also erasable in most cas es, it is impossible to recover the information once it has been erased. therefore, the system must be able to recognize the initial inva lid block(s) based on the initial invalid block information and creat e the initial invalid block table via the following suggested flow chart(figure 3). any intentional erasure of the initial invalid block information is prohibited. * check "ffh" at the column address figure 3. flow chart to create initial invalid block table. start set block address = 0 check "ffh" ? increment block address last block ? end no yes yes create (or update) no initial of the 1st and 2nd page in the block 517(x8 device) or 256 and 261(x16 device) invalid block(s) table
flash memory 15 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c K9K1208Q0C k9k1216q0c nand flash technical notes (continued) program flow chart start i/o 6 = 1 ? i/o 0 = 0 ? no * write 80h write address write data write 10h read status register program completed or r/b = 1 ? program error yes no yes error in write or read operation within its life time, the additional inva lid blocks may develop with nand flash memory . refer to the qualification report for t he actual data.the following possible failure modes shoul d be considered to implement a highly reli able system. in the case of status rea d fail- ure after erase or program, block replacement should be done. be cause program status fail during a page program does not affect the data of the other pages in the same block, block replac ement can be executed with a page-sized buffer by finding an erased empty block and reprogramming the current target data and copying the rest of the replaced block. in case of read, ecc must be employed. to improve the efficiency of memory space, it is recommended that the read or verification failure due to single bit error be reclaimed by ecc without any block replacement. the said additi onal block failure rate does no t include those reclaimed blocks. failure mode detection and countermeasure sequence write erase failure status read after erase --> block replacement program failure status read after program --> block replacement read single bit failure verify ecc -> ecc correction ecc : error correcting code --> hamming code etc. example) 1bit correction & 2bit detection : if program operation results in an error, map out the block including the page in error and copy the * target data to another block.
flash memory 16 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c K9K1208Q0C k9k1216q0c erase flow chart start i/o 6 = 1 ? i/o 0 = 0 ? no * write 60h write block address write d0h read status register or r/b = 1 ? erase error yes no : if erase operation results in an error, map out the failing block and replace it with another block. * erase completed yes read flow chart start verify ecc no write 00h write address read data ecc generation reclaim the error page read completed yes nand flash technical notes (continued) block replacement * step1 when an error happens in the nth page of the bl ock ?a? during erase or program operation. * step2 copy the nth page data of the block ?a? in the buffer memory to the nth page of another free block. (block ?b?) * step3 then, copy the data in the 1st ~ (n-1)th page to the same location of the block ?b?. * step4 do not further erase block ?a? by creating an ?i nvalid block? table or other appropriate scheme. buffer memory of the controller. 1st block a block b (n-1)th nth (page) 1 2 { 1st (n-1)th nth (page) { an error occurs.
flash memory 17 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c K9K1208Q0C k9k1216q0c 00h (1) command input sequence for programming ?a? area address / data input 80h 10h 00h 80h 10h address / data input the address pointer is set to ?a? area(0~255), and sustained 01h (2) command input sequence for programming ?b? area address / data input 80h 10h 01h 80h 10h address / data input ?b?, ?c? area can be programmed. it depends on how many data are inputted. ?01h? command must be rewritten before every program operation the address pointer is set to ?b? area(256~511), and will be reset to ?a? area after every program operation is executed. 50h (3) command input sequence for programming ?c? area address / data input 80h 10h 50h 80h 10h address / data input only ?c? area can be programmed. ?50h? command can be omitted. the address pointer is set to ?c? area(512~527), and sustained ?00h? command can be omitted. it depends on how many data are inputted. ?a?,?b?,?c? area can be programmed. pointer operation of k9k1208x0c(x8) table 2. destination of the pointer command pointer position area 00h 01h 50h 0 ~ 255 byte 256 ~ 511 byte 512 ~ 527 byte 1st half array(a) 2nd half array(b) spare array(c) "a" area 256 byte (00h plane) "b" area (01h plane) "c" area (50h plane) 256 byte 16 byte "a" "b" "c" internal page register pointer select commnad (00h, 01h, 50h) pointer figure 4. block diagram of pointer operation samsung nand flash has three address pointer commands as a subs titute for the two most significant column addresses. ?00h? command sets the pointer to ?a? area(0~255byte), ?01h? command se ts the pointer to ?b? area(256~511byte), and ?50h? command set s the pointer to ?c? area(512~527byte). with these commands, the starting column address can be set to any of a whole page(0~527byte). ?00h? or ?50h? is sustained until another addr ess pointer command is inputted. ?01h? command, however, is effe ctive only for one operation. after any operation of read, program, eras e, reset, power_up is executed once with ?01h? command, the address pointer returns to ?a? area by itself. to program data st arting from ?a? or ?c? area, ?00h? or ?50h? command must be in putted before ?80h? command is written. a complete read operation prior to ?80h? command is not necessary. to program data starting fr om ?b? area, ?01h? command must be inputt ed right before ?80h? command is written.
flash memory 18 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c K9K1208Q0C k9k1216q0c samsung nand flash has two address pointer commands as a substitute for the most significant column address. ?00h? command sets the pointer to ?a? area(0~255word), and ?50h? command sets the pointer to ?b? area(256~263word). with these commands, the starting column address can be set to any of a whole page(0~ 263word). ?00h? or ?50h? is su stained until another address pointer com- mand is inputted. to program data starting from ?a? or ?b? ar ea, ?00h? or ?50h? command must be inputted before ?80h? command i s writ- ten. a complete read operation prior to ?80h? command is not necessary. 00h (1) command input sequence for programming ?a? area address / data input 80h 10h 00h 80h 10h address / data input the address pointer is set to ?a? area(0~255), and sustained 50h (2) command input sequence for programming ?b? area address / data input 80h 10h 50h 80h 10h address / data input only ?b? area can be programmed. ?50h? command can be omitted. the address pointer is set to ?b? area(256~263), and sustained ?00h? command can be omitted. it depends on how many data are inputted. ?a?,?b? area can be programmed. pointer operation of k9k1216x0c(x16) table 3. destination of the pointer command pointer position area 00h 50h 0 ~ 255 word 256 ~ 263 word main array(a) spare array(b) "a" area 256 word (00h plane) "b" area (50h plane) 8 word "a" "b" internal page register pointer select command (00h, 50h) pointer figure 5. block diagram of pointer operation
flash memory 19 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c K9K1208Q0C k9k1216q0c system interface using ce don?t-care. ce we t wp t ch t cs start add.(4cycle) 80h data input ce cle ale we data input ce don?t-care 10h for an easier system interface, ce may be inactive during the data-loading or sequen tial data-reading as shown below. the internal 528byte(x8 device), 264word(x16 device) page registers are utiliz ed as seperate buffers for this operation and the system desig n gets more flexible. in addition, for voice or audio applications which use sl ow cycle time on the order of u-seconds, de-activating ce during the data-loading and reading would provide si gnificant savings in power consumption. start add.(4cycle) 00h ce cle ale we data output(sequential) ce don?t-care r/b t r re figure 6. program operation with ce don?t-care. figure 7. read operation with ce don?t-care. i/ox i/ox t cea out t rea ce re i/o 0 ~ 15 t oh
flash memory 20 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c K9K1208Q0C k9k1216q0c command latch cycle ce we cle ale i/ox command t cls t cs t clh t ch t wp t als t alh t ds t dh note : 1. i/o8~15 must be set to "0" during command or address input. i/o8~15 are used only for data bus. device i/o data i/ox data in/out k9k1208x0c(x8 device) i/o 0 ~ i/o 7 ~528byte k9k1216x0c(x16 device) i/o 0 ~ i/o 15 1) ~264word address latch cycle ce we cle ale i/o x a0~a7 t cls t cs t wc t wp t als t ds t dh t alh t als t wh t wc t wp t ds t dh t alh t als t wh t wc t wp t ds t dh t alh t als t wh t alh t ds t dh t wp a9~a16 a17~a24 a25 t ch
flash memory 21 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c K9K1208Q0C k9k1216q0c input data latch cycle ce cle we din 0 din 1 din n ale t als t clh t wc t ch t ds t dh t ds t dh t ds t dh t wp t wh t wp t wp serial access cycle after read (cle=l, we =h, ale=l) re ce r/b dout dout dout t rc t rea t rr t oh t rea t reh t rea t oh t rhz* notes : transition is measured 200mv from steady state voltage with load. this parameter is sampled and not 100% tested. i/ox i/ox t rhz* t chz* t rp
flash memory 22 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c K9K1208Q0C k9k1216q0c status read cycle ce we cle re i/ox 70h status output t clr t clh t cs t wp t ch t ds t dh t rea t ir t oh t oh t whr1 t cea t cls t rhz t chz t chz t oh read1 operation (read one page) x8 device : m = 528 , read cmd = 00h or 01h x16 device : m = 264 , read cmd = 00h 1) ce cle r/b i/o x we ale re busy 00h or 01h a 0 ~ a 7 a 9 ~ a 16 a 17 ~ a 24 dout n dout n+1 dout n+2 column address page(row) address t wb t ar t r t rc t rhz t rr dout m t wc a 25 n address t oh
flash memory 23 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c K9K1208Q0C k9k1216q0c read1 operation (intercepted by ce ) ce cle r/b i/o x we ale re busy 00h or 01h a 0 ~ a 7 a 9 ~ a 16 a 17 ~ a 24 dout n dout n+1 dout n+2 page(row) address address column t wb t ar t chz t r t rr t rc a 25 t oh read2 operation (read one page) ce cle r/b i/o x we ale re 50h a 0 ~ a 7 a 9 ~ a 16 a 17 ~ a 24 dout n+m m address n+m t ar t r t wb t rr a 0 ~a 3 : valid address a 4 ~a 7 : don t care a 25 selected row start address m 512 16
flash memory 24 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c K9K1208Q0C k9k1216q0c page program operation ce cle r/b i/o x we ale re 80h 70h i/o 0 din n din 10h 527 a 0 ~ a 7 a 17 ~ a 24 a 9 ~ a 16 sequential data input command column address page(row) address 1 up to 528 byte data serial input program command read status command i/o 0 =0 successful program i/o 0 =1 error in program t prog t wb t wc t wc t wc a 25
flash memory 25 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c K9K1208Q0C k9k1216q0c copy-back program operation ce cle r/b i/o x we ale re 00h 70h i/o 0 8ah a 0 ~a 7 a 17 ~a 24 a 9 ~a 16 column address page(row) address read status command i/o 0 =0 successful program i/o 0 =1 error in program t prog t wb t wc a 0 ~a 7 a 17 ~a 24 a 9 ~a 16 column address page(row) address busy t wb t r busy a 25 a 25 10h copy-back data input command block erase operation (erase one block) ce cle r/b i/o x we ale re 60h a 17 ~ a 24 a 9 ~ a 16 auto block erase setup command erase command read status command i/o 0 =1 error in erase doh 70h i/o 0 busy t wb t bers i/o 0 =0 successful erase page(row) address t wc a 25
flash memory 26 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c K9K1208Q0C k9k1216q0c manufacture & device id read operation ce cle we ale re 90h read id command maker code device code 00h t rea address. 1cycle t ar i/ox ech device device device code* K9K1208Q0C 36h k9k1208d0c 76h k9k1208u0c 76h k9k1216q0c xx46h k9k1216d0c xx56h k9k1216u0c xx56h code*
flash memory 27 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c K9K1208Q0C k9k1216q0c device operation page read upon initial device power up, the device defaults to read1 mode. th is operation is also initiated by writing 00h to the command regis- ter along with three address cycles. once the command is latched, it does not need to be written for the following page read op era- tion. two types of operations are avai lable : random read, serial page read. the random read mode is enabled when the page address is changed. t he 528 bytes(x8 device) or 264 words(x16 device) of data within the selected page are transferred to the data registers in less than 10 s(t r ). the system controller can detect the completion of this data transfer(tr) by analyzing the output of r/b pin. once the data in a page is loaded into the registers, they may be read out in 50ns cycle time by sequentially pulsing re . high to low transitions of the re clock output the data starting from the selected column address up to the last column address[column 511/ 527(x8 devic e) 255 /263(x16 device) depending on the state of gnd input pin]. the way the read1 and read2 commands work is like a pointer set to either the main area or the spare area. the spare area of 51 2 ~527 bytes(x8 device) or 256~263 words(x16 device) may be sele ctively accessed by writing the read2 command with gnd input pin low. addresses a 0~ a 3 (x8 device) or a 0~ a 2 (x16 device) set the starting address of the spare area while addresses a 4 ~a 7 are ignored in x8 device case or a 3~ a 7 must be "l" in x16 device case. the read1 command is needed to move the pointer back to the main area. figures 8, 9 show typical sequence and timings for each read operation. figure 8. read1 operation start add.(4cycle) 00h x8 device : a 0 ~ a 7 & a 9 ~ a 25 data output(sequential) (00h command) data field spare field ce cle ale r/b we re t r main array (01h command) data field spare field 1st half array 2st half array note: 1) after data access on 2nd half array by 01h command, the start pointer is automatically moved to 1st half array (00h) at next cycle. 01h command is only av ailable on x8 device(k9k1208x0c). i/ox x16 device : a 0 ~ a 7 & a 9 ~ a 25 1)
flash memory 28 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c K9K1208Q0C k9k1216q0c figure 9. read2 operation 50h data output(sequential) spare field ce cle ale r/b we start add.(4cycle) re t r x8 device : a 0 ~ a 3 & a 9 ~ a 25 main array data field spare field x16 device : a 0 ~ a 2 & a 9 ~ a 25 x8 device : a 4 ~ a 7 don?t care x16 device : a 3 ~ a 7 are "l" i/ox
flash memory 29 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c K9K1208Q0C k9k1216q0c page program the device is programmed basically on a page basis, but it does allow multiple partia l page programing of a byte/word or consec utive bytes/words up to 528 (x8 device) or 264 (x16 device) , in a single page program cycle. the num ber of consecutive partial page program- ming operation within the same page without an intervening eras e operation should not exceed 2 for main array and 3 for spare a rray. the addressing may be done in any random order in a block. a page pr ogram cycle consists of a seri al data loading period in whi ch up to 528 bytes (x8 device) or 264 words (x16 device) of data may be loaded into the page register, followed by a non-volatile program- ming period where the loaded data is programmed into the appropriat e cell. about the pointer operation, please refer to the att ached technical notes. the serial data loading period begins by inputting the serial da ta input command(80h), followed by the three cycle address inpu t and then serial data loading. the words other than those to be programmed do not need to be loaded.the page program confirm com- mand(10h) initiates the programming process. writing 10h alone wi thout previously entering the serial data will not initiate th e pro- gramming process. the internal write contro ller automatically executes the algorithms and timings necessary for program and ver ify, thereby freeing the system controller for other tasks. once the program process starts, the read status register command may be entered, with re and ce low, to read the status register. the system contro ller can detect the completion of a program cycle by mon- itoring the r/b output, or the status bit(i/o 6) of the status register. only the read status command and reset command are valid while programming is in progress. when the page program is comple te, the write status bit(i/o 0) may be checked(figure 10). the internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. the command register remains i n read status command mode until another valid command is written to the command register. figure 10. program operation 80h r/b address & data input i/o 0 pass 10h 70h fail t prog copy-back program the copy-back program is configured to qui ckly and efficiently rewrite data stored in one page within the array to another page within the same array without utilizing an exte rnal memory. since the time-consuming s equently-reading and its re-loading cycles are removed, the system performance is improved. the benefit is es pecially obvious when a portion of a block is updated and the res t of the block also need to be copied to the newly assigned free bloc k. the operation for performing a copy-back is a sequential exe cution of page-read without burst-reading cycle and copying-program with the address of destination page. a normal read operation with "00h" command with the address of the source page move s the whole 528bytes/264words(x8 device:528bytes, x16 device:264words) data into the internal buffer. as soon as the flash returns to ready state, copy-back programming command "8ah " may be given with three address cycles of target page followed. the data stored in the internal buffer is then programmed direc tly into the memory cells of the destination page. once the copy-back pr ogram is finished, any additional partial page programming into the copied pages is prohibited before erase. since the memory array is internally partitioned into four different planes, copy-back program is allowed only within the same memory plane. thus, a14 and a25, the plane address, of source and destination page address must be the same. "when there is a program-failure at copy-back operation, error is reported by pass/fail status. but if the soure page has a bit error for charge loss, accumulated copy-back operations could also accumulate bit errors. for this reason, two bit ecc is recommended for copy-back operation." figure 11. copy-back program operation 00h r/b add.(4cycles) i/o 0 pass 8ah 70h fail t prog add.(4cycles) t r source address destination address i/ox i/ox
flash memory 30 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c K9K1208Q0C k9k1216q0c figure 12. block erase operation block erase the erase operation is done on a bl ock basis. block address loading is accomplished in three cycles initiated by an erase setup com- mand(60h). only address a 14 to a 25 is valid while a 9 to a 13 is ignored. the erase confirm co mmand(d0h) following the block address loading initiates the internal erasing proc ess. this two-step sequence of setup foll owed by execution command ensures that memo ry contents are not accidentally erased due to external noise conditions. at the rising edge of we after the erase confirm command input, the internal writ e controller handles erase and erase-verify. when the erase operation is completed, the write status bit( i/o 0) may be checked. figure 12 details the sequence. 60h block add. : a 9 ~ a 25 r/b address input(3cycle) i/o 0 pass d0h 70h fail t bers read status the device contains a status register which may be read to find out whether program or erase operation is completed, and whethe r the program or erase operation is comple ted successfully. after writing 70h command to the command register, a read cycle outpu ts the content of the status register to the i/o pins on the falling edge of ce or re , whichever occurs last. this two line control allows the system to poll the progress of each device in multiple memory connections even when r/b pins are common-wired. re or ce does not need to be toggled for updated status. refer to table 4 fo r specific status register definitions. the command register remains in status read mode until further commands are issued to i t. therefore, if the status re gister is read during a random read cycle, a read command(00h or 50h) should be given before seri al access cycle. table4. read status register definition i/o # status definition i/o 0 program / erase "0" : successful program / erase "1" : error in program / erase i/o 1 reserved for future use "0" i/o 2 "0" i/o 3 "0" i/o 4 "0" i/o 5 "0" i/o 6 device operation "0" : busy "1" : ready i/o 7 write protect "0" : protected "1" : not protected i/o 8~15 not use don?t care i/ox
flash memory 31 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c K9K1208Q0C k9k1216q0c figure 13. read id operation ce cle ale re we 90h 00h address. 1cycle maker code device code t cea t ar t rea read id the device contains a product ident ification mode, initiated by writing 90h to the command register, followed by an address inp ut of 00h. two read cycles sequentially output the manufacture code(ech), and the device code respectively. the command register remains in read id mode until further commands are issued to it. figure 13 shows the operation sequence. t whr1 figure 14. reset operation reset the device offers a reset feature, executed by writing ffh to the command register. w hen the device is in busy state during ran dom read, program or erase mode, the reset operation will abort thes e operations. the contents of memory cells being altered are no longer valid, as the data will be partially programmed or eras ed. the command register is cleared to wait for the next command, and the status register is cleared to value c0h when wp is high. refer to table 5 for device st atus after reset operation. if the device is already in reset state a new reset command will not be accepted by the command register. the r/b pin transitions to low for trst after the reset command is written. refer to figure 14 below. table5. device status after power-up after reset operation mode read 1 waiting for next command ffh r/b t rst ech device i/ox i/ox device device code* K9K1208Q0C 36h k9k1208d0c 76h k9k1208u0c 76h k9k1216q0c xx46h k9k1216d0c xx56h k9k1216u0c xx56h code*
flash memory 32 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c K9K1208Q0C k9k1216q0c block lock mode is enabled while lockpre pin state is high, which is to offer protection features for nand flash data. the bloc k lock mode is divided into unlock, lock, lock-tight operation. cons ecutive blocks protects data by allowing those blocks to be l ocked or lock-tighten with no latency. this block lock scheme offers two levels of protecti on. the first allows software control(comm and input method) of block locking that is useful for frequently ch anged data blocks, while the second requires hardware control(wp low pulse input method) before locking can be changed that is useful for protecting in frequently changed code blocks. the followings summarized the locking functionality. - all blocks are in a locked state on power -up. unlock sequence can unlock the locked blocks. - the lock-tight command lock s blocks and prevents from being unlocked. and lock-tight state can be returned to lock state only by hardware control(wp low pulse input). block lock mode - command sequence: lock block command(2ah) - all blocks default to locked by power-up and hardware control(wp low pulse input) - partial block lock is not available; lock block operation is based on all block unit - unlocked blocks can be locked by using the lock block command, and a lock blo ck?s status can be changed to unlock or lock-ti ght using the appropriate commands 1. block lock operation 1) lock > in high state of lockpre pin, block lock mode and power on auto read are enabled, otherwise it is regarded as nand flash without lockpre pin. ce cle we 2ah lock command i/ox wp
flash memory 33 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c K9K1208Q0C k9k1216q0c - command sequence: lock-tight block command(2ch) - lock-tighten blocks offer the user an addi tional level of write protection beyond t hat of a regular lock block. a block that is lock- tighten can?t have it?s state changed by soft ware control, only by hardware control(wp low pulse input); unlocking multi area is not available - only locked blocks can be lo ck-tighten by lock-tight command. 3) lock-tight - command sequence: unlock block command(23h) + st art block address + command(24h) + end block address - unlocked blocks can be programmed or erased. - an unlocked block?s status can be changed to the locked or lock-tighten state using the appropriate commands. - only one consecutive area can be released to unlock stat e from lock state; unlocking multi area is not available. - start block address must be nearer to the logica l lsb(least significant bit) than end blcok address. - one block is selected for unlocking block when start block address is same as end block address. 2) unlock ce cle we ale 23h unock command add.1 start block address 3cycles i/ox 24h add.2 end block address 3 cycles unlock command ce cle we 2ch lock-tight command i/ox wp wp add.3 add.1 add.2 add.3
flash memory 34 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c K9K1208Q0C k9k1216q0c program/erase operation(in locked or lock-tighten block) on the program or erase operation in locked or lock-tighten block, busy state holds 1~10 s( t lbsy) 60h(80h) r/b address(&data input) d0h(10h) t lbsy i/ox locked or lock-tighten block address unlock lock lock-tight power-up wp x = h & unlock block command (23h) + start block address + command (24h) + end block address block lock reset wp x = l (>100ns) block lock reset wp x = l (>100ns) wp x = h & lock block command (2ah) wp x = h & lock-tight block command (2ch) unlock unlock figure 15. state diagram of block lock lock-tight lock-tight block command (2ch) lock lock lock lock lock-tight wp x = h & wp x = h & unlock block command (23h) + start block address + command (24h) + end block address
flash memory 35 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c K9K1208Q0C k9k1216q0c block lock status can be read on a block basis, which may be read to find out whether designated block is available to be pro- grammed or erased. after writing 7ah command to the command regi ster. and block address to be checked, a read cycle outputs the content of the block lock status register to the i/o pins on the falling edge of ce or re , whichever occurs last. this two line control allows the system to poll the pr ogress of each device in multiple memory connections even when r/b pins are common-wired. re or ce does not need to be toggled for updated status. blcok lock status read is prohibited while the device is busy state. refer to table 6 for specific status regi ster definitions. the command register remains in block lock status read mode until fu rther commands are issued to it. in high state of lockpre pin, write protection status can be checked by block lock status read(7ah) while in low state by status read(70h). 2. block lock status read ce cle we ale re 7ah read block lock block lock status add.1 block address 3cycle i/ox dout add.2 table6. block lock status register definitions status command wp t whr2 add.3 io7~io3 io2(unlock) io1(lock) io0(lock-tight) read 1) block case x01 0 read 2) block case x11 0 read 3) block case x00 1 read 4) block case x10 1 (1)lock (2)unlock (3)lock-tight (4)unlock (1)lock (3)lock-tight (1)lock (2)unlock (3)lock-tight
flash memory 36 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c K9K1208Q0C k9k1216q0c power-on auto-read the device is designed to offer automatic reading of the first page without command and addres s input sequence during power-on. an internal voltage detector enables auto-page read functions wh en vcc reaches about 1.8v. lockpre pin controls activation of auto- page read function. auto-page read function is enabl ed only when lockpre pin is logic high state . serial access may be done after power-on without latency. power-on auto r ead mode is available only on 3.3v device(k9k12xxu0c). figure 16. power-on auto-read (3.3v device only) v cc ce cle i/o x ale re we 1st ~ 1.8v lockpre r/b 2nd 3rd .... n th t r
flash memory 37 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c K9K1208Q0C k9k1216q0c ready/busy the device has a r/b output that provides a hardware method of indica ting the completion of a page program, erase and random read completion. the r/b pin is normally high but transition s to low after program or erase command is written to the command regis- ter or random read is started after address loading. it returns to high when the intern al controller has finished the operation . the pin is an open-drain driver thereby allowing two or more r/b outputs to be or-tied. because pull-up resistor value is related to tr(r/b ) and current drain during busy(ibusy) , an appropriate value can be obt ained with the following reference chart(fig 17). its value can be determined by the following guidance. v cc r/b open drain output device gnd rp figure 17. rp vs tr ,tf & rp vs ibusy ibusy busy ready vcc voh tf tr vol c l 1.8v device - v ol : 0.1v, v oh : vcc q -0.1v 3.3v device - v ol : 0.4v, v oh : 2.4v 2.65v device - v ol : 0.4v, v oh : vcc q -0.4v
flash memory 38 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c K9K1208Q0C k9k1216q0c tr,tf [s] ibusy [a] rp(ohm) ibusy tr @ vcc = 3.3v, ta = 25 c , c l = 100pf 1k 2k 3k 4k 100n 200n 300n 3m 2m 1m 100 tf 200 300 400 3.6 3.6 3.6 3.6 2.4 1.2 0.8 0.6 rp(min, 1.8v part) = v cc (max.) - v ol (max.) i ol + i l = 1.85v 3ma + i l where i l is the sum of the input currents of all devices tied to the r/b pin. rp value guidance rp(max) is determined by maxi mum permissible limit of tr rp(min, 3.3v part) = v cc (max.) - v ol (max.) i ol + i l = 3.2v 8ma + i l tr,tf [s] ibusy [a] rp(ohm) ibusy tr @ vcc = 1.8v, ta = 25 c , c l = 30pf 1k 2k 3k 4k 100n 200n 300n 3m 2m 1m 30 tf 60 90 120 1.7 1.7 1.7 1.7 1.7 0.85 0.57 0.43 rp(min, 2.65v part) = v cc (max.) - v ol (max.) i ol + i l = 2.5v 3ma + i l tr,tf [s] ibusy [a] rp(ohm) ibusy tr @ vcc = 2.65v, ta = 25 c , c l = 30pf 1k 2k 3k 4k 100n 200n 300n 3m 2m 1m 30 tf 60 90 120 2.3 2.3 2.3 2.3 2.3 1.1 0.75 0.55
flash memory 39 k9k1216d0c k9k1216u0c k9k1208d0c k9k1208u0c K9K1208Q0C k9k1216q0c the device is designed to offer protection from any involuntary program/erase duri ng power-transitions. an internal voltage det ector disables all functions whenev er vcc is below about 1.1v(1.8v device), 1.8v(2.65v device), 2v(3.3v device). wp pin provides hard- ware protection and is recommended to be kept at v il during power-up and power-down and recovery time of minimum 10 s is required before internal circuit gets ready for any command se quences as shown in figure 18. the two step command sequence for program/erase provides additional software protection. figure 18. ac waveforms for power transition v cc wp high 1.8v device : ~ 1.5v we data protection & power up sequence 3.3v device : ~ 2.5v 1.8v device : ~ 1.5v 3.3v device : ~ 2.5v 10 s 2.65v device : ~ 2.0v 2.65v device : ~ 2.0v

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